The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Jun. 10, 2008
Michael L. Choate, Round Rock, TX (US);
Mark D. Nicol, Austin, TX (US);
Heather L. Hanson, Austin, TX (US);
Michael J. Borsch, Austin, TX (US);
Arthur M. Ryan, Round Rock, TX (US);
Chandrakant Pandya, Pflugerville, TX (US);
Michael L. Choate, Round Rock, TX (US);
Mark D. Nicol, Austin, TX (US);
Heather L. Hanson, Austin, TX (US);
Michael J. Borsch, Austin, TX (US);
Arthur M. Ryan, Round Rock, TX (US);
Chandrakant Pandya, Pflugerville, TX (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.