The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2011

Filed:

Dec. 22, 2005
Applicants:

Jong-seo Hong, Gyeonggi-do, KR;

Jeong-sic Jeon, Gyeonggi-do, KR;

Chun-suk Suh, Gyeonggi-do, KR;

Yoo-sang Hwang, Gyeonggi-do, KR;

Inventors:

Jong-Seo Hong, Gyeonggi-do, KR;

Jeong-Sic Jeon, Gyeonggi-do, KR;

Chun-Suk Suh, Gyeonggi-do, KR;

Yoo-Sang Hwang, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.


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