The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Dec. 19, 2008
Applicants:

Jonathan W Greene, Palo Alto, CA (US);

Gregory Bakker, San Jose, CA (US);

Vidyadhara Bellippady, San Jose, CA (US);

Volker Hecht, Barsinghausen, DE;

Theodore Speers, San Jose, CA (US);

Inventors:

Jonathan W Greene, Palo Alto, CA (US);

Gregory Bakker, San Jose, CA (US);

Vidyadhara Bellippady, San Jose, CA (US);

Volker Hecht, Barsinghausen, DE;

Theodore Speers, San Jose, CA (US);

Assignee:

Actel Corporation, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.


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