The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Aug. 17, 2010
Chuan-cheng Cheng, Fremont, CA (US);
Choy Hing LI, Saratoga, CA (US);
Shiann-ming Liou, Campbell, CA (US);
Chuan-Cheng Cheng, Fremont, CA (US);
Choy Hing Li, Saratoga, CA (US);
Shiann-Ming Liou, Campbell, CA (US);
Marvell International Ltd., Hamilton, BM;
Abstract
Methods for fabricating and testing integrated circuit devices and systems. The integrated circuit device generally includes two semiconductor dies. The first die has little or no I/O or ESD protection, and the second die includes at least one exposed terminal in electrical communication with one or more terminals on the first die, at least one I/O circuit in electrical communication with one or more terminals on the second die, and at least one I/O terminal in electrical communication with the I/O circuit(s). The method of forming an integrated circuit includes aligning at least one of the exposed terminals on the first die with at least one of the exposed terminals on the second die, and forming at least one electrical junction between them such that the exposed terminal(s) on the first die is/are in electrical communication with an I/O circuit and an I/O terminal on the second die. The method of testing a semiconductor die includes placing the semiconductor die into a predetermined position for testing, placing a tester probe tip in contact with a subset of the exposed terminals on the first die, the probe head having an ESD protection structure in electrical communication with the probe tip, and testing the die.