The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Feb. 21, 2008
Applicants:

Byung-yong Choi, Seoul, KR;

Choong-ho Lee, Seongnam-si, KR;

Kyu-charn Park, Byeongtaek-si, KR;

Inventors:

Byung-Yong Choi, Seoul, KR;

Choong-Ho Lee, Seongnam-si, KR;

Kyu-Charn Park, Byeongtaek-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.


Find Patent Forward Citations

Choi, Byung-Yong. (2011). Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers (U.S. Patent No. 7883929). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7883929

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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