The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2011
Filed:
Dec. 08, 2008
Ming-dou Ker, Hsinchu County, TW;
Yuan-wen Hsiao, Tai-Chung, TW;
Chang-tzu Wang, Taipei, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
National Chiao-Tung University, Hsinchu, TW;
Abstract
An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first Ndiffusion region, a first Pdiffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second Ndiffusion region electrically connected to the first Pdiffusion region, a second Pdiffusion region electrically connected to the first Ndiffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.