The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Dec. 01, 2008
Shotaro Kobayashi, Tokyo, JP;
Katsuhiro Kitagawa, Tokyo, JP;
Shotaro Kobayashi, Tokyo, JP;
Katsuhiro Kitagawa, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.