The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2011

Filed:

Oct. 16, 2009
Applicants:

Pankaj Kumar, Karnataka, IN;

Pramod Elamannu Parameswaran, Karnataka, IN;

Makeshwar Kothandaraman, Whitehall, PA (US);

Vani Deshpande, Karnataka, IN;

John Kriz, Palmerton, PA (US);

Inventors:

Pankaj Kumar, Karnataka, IN;

Pramod Elamannu Parameswaran, Karnataka, IN;

Makeshwar Kothandaraman, Whitehall, PA (US);

Vani Deshpande, Karnataka, IN;

John Kriz, Palmerton, PA (US);

Assignee:

LSI Corporation, Milpjtas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.


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