The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Mar. 13, 2007
Liu Yaocheng, Elmsford, NY (US);
Ricardo A. Donaton, Cortlandt Manor, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Liu Yaocheng, Elmsford, NY (US);
Ricardo A. Donaton, Cortlandt Manor, NY (US);
Kern Rim, Yorktown Heights, NY (US);
International Business Machines Corporation, New York, NY (US);
Abstract
A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile