The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2011
Filed:
Oct. 28, 2009
Jeong Tae Kim, Kyoungki-do, KR;
Baek Mann Kim, Kyoungki-do, KR;
Soo Hyun Kim, Seoul, KR;
Young Jin Lee, Kyoungki-do, KR;
Dong Ha Jung, Kyoungki-do, KR;
Jeong Tae Kim, Kyoungki-do, KR;
Baek Mann Kim, Kyoungki-do, KR;
Soo Hyun Kim, Seoul, KR;
Young Jin Lee, Kyoungki-do, KR;
Dong Ha Jung, Kyoungki-do, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.