The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2011
Filed:
Aug. 19, 2009
Eduard A. Cartier, New York, NY (US);
Steven J. Koester, Ossining, NY (US);
Kingsuk Maitra, Yorktown Heights, NY (US);
Amlan Majumdar, White Plains, NY (US);
Renee T. MO, Briarcliff Manor, NY (US);
Eduard A. Cartier, New York, NY (US);
Steven J. Koester, Ossining, NY (US);
Kingsuk Maitra, Yorktown Heights, NY (US);
Amlan Majumdar, White Plains, NY (US);
Renee T. Mo, Briarcliff Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.