The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Feb. 25, 2002
Matthias A. Blumrich, Ridgefield, CT (US);
Dong Chen, Croton on Hudson, NY (US);
Paul W. Coteus, Yorktown Heights, NY (US);
Alan G. Gara, Mount Kisco, NY (US);
Mark E. Giampapa, Irvington, NY (US);
Philip Heidelberger, Cortlandt Manor, NY (US);
Dirk Hoenicke, Ossining, NY (US);
Martin Ohmacht, Yorktown Heights, NY (US);
Matthias A. Blumrich, Ridgefield, CT (US);
Dong Chen, Croton on Hudson, NY (US);
Paul W. Coteus, Yorktown Heights, NY (US);
Alan G. Gara, Mount Kisco, NY (US);
Mark E. Giampapa, Irvington, NY (US);
Philip Heidelberger, Cortlandt Manor, NY (US);
Dirk Hoenicke, Ossining, NY (US);
Martin Ohmacht, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.