The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Jul. 25, 2008
Applicants:

Hideyuki Ono, Tokyo, JP;

Toru Fujioka, Tokyo, JP;

Masahito Numanami, Tokyo, JP;

Inventors:

Hideyuki Ono, Tokyo, JP;

Toru Fujioka, Tokyo, JP;

Masahito Numanami, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/191 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10Ω or so, for example, the resistor is set to about a few Ω to about 100Ω. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.


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Ono, Hideyuki. (2011). Semiconductor integrated circuit device (U.S. Patent No. 7868699). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7868699

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