The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Nov. 16, 2005
Applicants:

Kuo-ting Lee, Yonghe, TW;

You-kuo Wu, Sijhih, TW;

Fu-hsin Chen, Jhudong Township, Hsinchu County, TW;

An-ming Chiang, Hsinchu, TW;

Inventors:

Kuo-Ting Lee, Yonghe, TW;

You-Kuo Wu, Sijhih, TW;

Fu-Hsin Chen, Jhudong Township, Hsinchu County, TW;

An-Ming Chiang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.


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