The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Jun. 28, 2007
Haining S. Yang, Wappingers Falls, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Byeong Y. Kim, LaGrangeville, NY (US);
Junedong Lee, Hopewell Junction, NY (US);
Gaku Sudo, Yokohama, JP;
Haining S. Yang, Wappingers Falls, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Byeong Y. Kim, LaGrangeville, NY (US);
Junedong Lee, Hopewell Junction, NY (US);
Gaku Sudo, Yokohama, JP;
International Business Machines Corporation, Armonk, NY (US);
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator ('SOI') substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.