The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Aug. 01, 2008
Applicants:

Choong-ho Lee, Seongnam-si, KR;

Jai-hyuk Song, Seoul, KR;

Dong-uk Choi, Seongnam-si, KR;

Suk-kang Sung, Seongnam-si, KR;

Inventors:

Choong-Ho Lee, Seongnam-si, KR;

Jai-Hyuk Song, Seoul, KR;

Dong-Uk Choi, Seongnam-si, KR;

Suk-Kang Sung, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.


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