The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Apr. 22, 2010
Minghao Shen, Sunnyvale, CA (US);
Fred Cheung, San Jose, CA (US);
Ning Cheung, San Jose, CA (US);
Wei Zheng, Santa Clara, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Chih-yuh Yang, San Jose, CA (US);
Minghao Shen, Sunnyvale, CA (US);
Fred Cheung, San Jose, CA (US);
Ning Cheung, San Jose, CA (US);
Wei Zheng, Santa Clara, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Chih-Yuh Yang, San Jose, CA (US);
Spansion, LLC, Sunnyvale, CA (US);
Abstract
Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.