The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7865856 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 04, 2011

Filed:

Mar. 12, 2008
Applicants:

Andrew B. Kahng, Del Mar, CA (US);

Puneet Gupta, Los Angeles, CA (US);

Saumil Shah, Santa Clara, CA (US);

Inventors:

Andrew B. Kahng, Del Mar, CA (US);

Puneet Gupta, Los Angeles, CA (US);

Saumil Shah, Santa Clara, CA (US);

Assignee:

Tela Innovations, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.


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Kahng, Andrew. (2011). System and method for performing transistor-level static performance analysis using cell-level static analysis tools (U.S. Patent No. 7865856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7865856

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