The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7864611 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 04, 2011

Filed:

Oct. 30, 2009
Applicants:

Hee Bok Kang, Cheongju-si, KR;

Jin Hong an, Yongin-si, KR;

Sung Joo Hong, Seoul, KR;

Suk Kyoung Hong, Gwacheon-si, KR;

Inventors:

Hee Bok Kang, Cheongju-si, KR;

Jin Hong An, Yongin-si, KR;

Sung Joo Hong, Seoul, KR;

Suk Kyoung Hong, Gwacheon-si, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.


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