The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Nov. 14, 2007
Fulong Zhang, Allentown, PA (US);
Zhen Chen, Allentown, PA (US);
William Andrews, Macungie, PA (US);
Barry Britton, Allentown, PA (US);
Fulong Zhang, Allentown, PA (US);
Zhen Chen, Allentown, PA (US);
William Andrews, Macungie, PA (US);
Barry Britton, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.