The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Sep. 30, 2008
Matthias Goldbach, Dresden, DE;
Jessica Hartwich, Dresden, DE;
Lars Dreeskornfeld, Munich, DE;
Arnd Scholz, Dresden, DE;
Tobias Mono, Dresden, DE;
Matthias Goldbach, Dresden, DE;
Jessica Hartwich, Dresden, DE;
Lars Dreeskornfeld, Munich, DE;
Arnd Scholz, Dresden, DE;
Tobias Mono, Dresden, DE;
Qimonda AG, Munich, DE;
Abstract
A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.