The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7859012 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 28, 2010

Filed:

Aug. 10, 2009
Applicant:

Maxim Ershov, San Jose, CA (US);

Inventor:

Maxim Ershov, San Jose, CA (US);

Assignee:

T-RAM Semiconductor, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with an embodiment of the present invention, a semiconductor memory device includes an array of thyristor-based memory formed in a silicon-on-insulator (SOI) supporting substrate. A portion of the supporting structure of the SOI substrate has a density of dopants sufficient to assist delivery of a bias to the backside of an insulating layer beneath a thyristor of the thyristor-based semiconductor memory. By enabling biasing of the substrate at the backside of the insulating layer beneath the thyristor, a back-gate control is available for controlling or compensating the gain of a component bipolar device of the thyristor with respect to temperature.


Find Patent Forward Citations

Ershov, Maxim. (2010). Thyristor-based semiconductor memory device with back-gate bias (U.S. Patent No. 7859012). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7859012

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