The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2010
Filed:
Apr. 04, 2008
Eduard A. Cartier, New York, NY (US);
Matthew W. Copel, Yorktown Heights, NY (US);
Martin M. Frank, Bronx, NY (US);
Evgeni P. Gousev, Saratoga, CA (US);
Paul C. Jamison, Hopewell Junction, NY (US);
Rajarao Jammy, Austin, TX (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Eduard A. Cartier, New York, NY (US);
Matthew W. Copel, Yorktown Heights, NY (US);
Martin M. Frank, Bronx, NY (US);
Evgeni P. Gousev, Saratoga, CA (US);
Paul C. Jamison, Hopewell Junction, NY (US);
Rajarao Jammy, Austin, TX (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiOand a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.