The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2010
Filed:
May. 07, 2007
Tomohiro Kitano, Tokyo, JP;
Tomohiro Kitano, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A design method for a semiconductor integrated circuit includes a first step (S) of grouping pins that configure a same net into a plurality of groups; a second step (S) of defining sub-trunk wirings mutually connecting the pins that belong to a same group; a third step (S) of defining a main trunk wiring substantially parallel to the sub-trunk wirings; and a fourth step (S) of defining a lead-in wiring connecting at least the main trunk wiring and the sub-trunk wirings. Thus, a plurality of pins are grouped, and the groups are mutually connected by the sub-trunk wirings, making it possible to decrease the number of the lead-in wirings. Thereby, even when the number of nets is large relative to the area of a layout region, a probability of occurrence of nets where automatic wiring is impossible can be greatly reduced.