The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2010
Filed:
Jun. 30, 2008
Jason R. Baumgartner, Austin, TX (US);
Hari Mony, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
Jiazhao Xu, Mount Kisco, NY (US);
Jason R. Baumgartner, Austin, TX (US);
Hari Mony, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
Jiazhao Xu, Mount Kisco, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N') of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.