The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2010
Filed:
Jan. 30, 2008
Yasuyuki Yanase, Gifu, JP;
Yoshio Okayama, Gifu, JP;
Kiyoshi Shibata, Gifu, JP;
Yasunori Inoue, Ogaki, JP;
Hideki Mizuhara, Ichinomiya, JP;
Ryosuke Usui, Ichinomiya, JP;
Tetsuya Yamamoto, Hashima, JP;
Masurao Yoshii, Sano, JP;
Yasuyuki Yanase, Gifu, JP;
Yoshio Okayama, Gifu, JP;
Kiyoshi Shibata, Gifu, JP;
Yasunori Inoue, Ogaki, JP;
Hideki Mizuhara, Ichinomiya, JP;
Ryosuke Usui, Ichinomiya, JP;
Tetsuya Yamamoto, Hashima, JP;
Masurao Yoshii, Sano, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Abstract
An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.