The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Jul. 17, 2008
Tae-jin Hwang, Ichon, KR;
Kun-woo Park, Ichon, KR;
Yong-ju Kim, Ichon, KR;
Hee-woong Song, Ichon, KR;
Ic-su OH, Ichon, KR;
Hyung-soo Kim, Ichon, KR;
Hae-rang Choi, Ichon, KR;
Ji-wang Lee, Ichon, KR;
Tae-Jin Hwang, Ichon, KR;
Kun-Woo Park, Ichon, KR;
Yong-Ju Kim, Ichon, KR;
Hee-Woong Song, Ichon, KR;
Ic-Su Oh, Ichon, KR;
Hyung-Soo Kim, Ichon, KR;
Hae-Rang Choi, Ichon, KR;
Ji-Wang Lee, Ichon, KR;
Hynix Semiconductor Inc., , KR;
Abstract
A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.