The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Nov. 29, 2007
Applicants:

Satoshi Hikida, Nara, JP;

Takuya Otabe, Fukuyama, JP;

Hisashi Yonemoto, Fukuyama, JP;

Inventors:

Satoshi Hikida, Nara, JP;

Takuya Otabe, Fukuyama, JP;

Hisashi Yonemoto, Fukuyama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.


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