The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Jun. 08, 2007
Xiangfeng Duan, Mountain View, CA (US);
Chunming Niu, Palo Alto, CA (US);
Stephen A. Empedocles, Menlo Park, CA (US);
Linda T. Romano, Sunnyvale, CA (US);
Jian Chen, Mountain View, CA (US);
Vijendra Sahi, Menlo Park, CA (US);
Lawrence Bock, Encinitas, CA (US);
David P. Stumbo, Belmont, CA (US);
J. Wallace Parce, Palo Alto, CA (US);
Jay L. Goldman, Mountain View, CA (US);
Xiangfeng Duan, Mountain View, CA (US);
Chunming Niu, Palo Alto, CA (US);
Stephen A. Empedocles, Menlo Park, CA (US);
Linda T. Romano, Sunnyvale, CA (US);
Jian Chen, Mountain View, CA (US);
Vijendra Sahi, Menlo Park, CA (US);
Lawrence Bock, Encinitas, CA (US);
David P. Stumbo, Belmont, CA (US);
J. Wallace Parce, Palo Alto, CA (US);
Jay L. Goldman, Mountain View, CA (US);
Nanosys, Inc., Palo Alto, CA (US);
Abstract
A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.