The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2010
Filed:
May. 19, 2005
Xiang Zou, Portland, OR (US);
Hong Wang, Fremont, CA (US);
Scott Dion Rodgers, Hillsboro, OR (US);
Darrell D. Boggs, Aloha, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
Shivanandan Kaushik, Portland, OR (US);
Anil Aggarwal, Portland, OR (US);
Ittai Anati, Haifa, IL;
Doron Orenstein, Haifa, IL;
Per Hammarlund, Hillsboro, OR (US);
John Shen, San Jose, CA (US);
Larry O. Smith, Beaverton, OR (US);
James B. Crossland, Banks, OR (US);
Chris J. Newburn, South Beloit, IL (US);
Xiang Zou, Portland, OR (US);
Hong Wang, Fremont, CA (US);
Scott Dion Rodgers, Hillsboro, OR (US);
Darrell D. Boggs, Aloha, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
Shivanandan Kaushik, Portland, OR (US);
Anil Aggarwal, Portland, OR (US);
Ittai Anati, Haifa, IL;
Doron Orenstein, Haifa, IL;
Per Hammarlund, Hillsboro, OR (US);
John Shen, San Jose, CA (US);
Larry O. Smith, Beaverton, OR (US);
James B. Crossland, Banks, OR (US);
Chris J. Newburn, South Beloit, IL (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.