The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2010

Filed:

May. 01, 2007
Applicants:

Roman Surgutchik, Santa Clara, CA (US);

Robert William Chapman, Mountain View, CA (US);

David G. Reed, Saratoga, CA (US);

Brad W. Simeral, San Francisco, CA (US);

Inventors:

Roman Surgutchik, Santa Clara, CA (US);

Robert William Chapman, Mountain View, CA (US);

David G. Reed, Saratoga, CA (US);

Brad W. Simeral, San Francisco, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.


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