The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2010
Filed:
Jul. 14, 2006
Yusaku Ono, Tokyo, JP;
Osamu Suga, Tokyo, JP;
Kazuyuki Sakata, Tokyo, JP;
Hirofumi Taguchi, Osaka, JP;
Yushi Okuno, Kanagawa, JP;
Toshiaki Sugioka, Kanagawa, JP;
Daisuke Kondo, Kawasaki, JP;
Yusaku Ono, Tokyo, JP;
Osamu Suga, Tokyo, JP;
Kazuyuki Sakata, Tokyo, JP;
Hirofumi Taguchi, Osaka, JP;
Yushi Okuno, Kanagawa, JP;
Toshiaki Sugioka, Kanagawa, JP;
Daisuke Kondo, Kawasaki, JP;
Renesas Electronics Corporation, Kawasaki-Shi, Kanagawa, JP;
Panasonic Corporation, Kodami-Shi, Osaka, JP;
Fujitsu Microelectronics Limited, Shinjuku-Ku, Tokyo, JP;
Kabushiki Kaisha Toshiba, Minato-Ku, Tokyo, JP;
Abstract
According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.