The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
May. 21, 2009
Yasuhiro Takai, Tokyo, JP;
Yasuhiro Takai, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.