The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2010
Filed:
Apr. 30, 2007
Matthew V. Kaufmann, Morgan Hill, CA (US);
Teck Yang Tan, Singapore, SG;
Matthew V. Kaufmann, Morgan Hill, CA (US);
Teck Yang Tan, Singapore, SG;
Broadcom Corporation, Irvine, CA (US);
Abstract
Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.