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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7833849 B1

PDFFull Text
Expired
Date of Patent:
Nov. 16, 2010

Filed:

Dec. 30, 2005

Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode

Applicants:

Alessandro C. Callegari, Yorktown Heights, NY (US);

Tze-chiang Chen, Yorktown Heights, NY (US);

Michael P. Chudzik, Danbury, CT (US);

Bruce B. Doris, Brewster, NY (US);

Young-hee Kim, Yorktown Heights, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi K. Paruchuri, New York, NY (US);

Michelle L. Steen, Danbury, CT (US);

Ying Zhang, Yorktown Heights, NY (US);

Inventors:

Alessandro C. Callegari, Yorktown Heights, NY (US);

Tze-Chiang Chen, Yorktown Heights, NY (US);

Michael P. Chudzik, Danbury, CT (US);

Bruce B. Doris, Brewster, NY (US);

Young-Hee Kim, Yorktown Heights, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi K. Paruchuri, New York, NY (US);

Michelle L. Steen, Danbury, CT (US);

Ying Zhang, Yorktown Heights, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

Louis J. Percello, Esq.

Primary Examiner:

Thomas L Dickey

Int. Cl.
CPC ...
H01L 21/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.

Find Patent Forward Citations

Callegari, Alessandro. (2010). Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode (U.S. Patent No. 7833849). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7833849

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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