The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2010
Filed:
Jan. 20, 2006
Neung-ho Cho, Gyeonggi-do, KR;
Sung-wook Kim, Gyeonggi-do, KR;
Yong-kil Park, Gyeonggi-do, KR;
Bae-hyoun Jung, Gyeonggi-do, KR;
Dong-yub Chae, Seoul, KR;
Youn-soo Choi, Gyeonggi-do, KR;
Neung-Ho Cho, Gyeonggi-do, KR;
Sung-Wook Kim, Gyeonggi-do, KR;
Yong-Kil Park, Gyeonggi-do, KR;
Bae-Hyoun Jung, Gyeonggi-do, KR;
Dong-Yub Chae, Seoul, KR;
Youn-Soo Choi, Gyeonggi-do, KR;
Abstract
The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.