The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2010

Filed:

May. 25, 2005
Applicants:

Koichi Takeda, Minato-ku, JP;

Masahiro Nomura, Minato-ku, JP;

Kiyoshi Takeuchi, Minato-ku, JP;

Hitoshi Wakabayashi, Minato-ku, JP;

Shigeharu Yamagami, Minato-ku, JP;

Risho Koh, Minato-ku, JP;

Koichi Terashima, Minato-ku, JP;

Katsuhiko Tanaka, Minato-ku, JP;

Masayasu Tanaka, Minato-ku, JP;

Inventors:

Koichi Takeda, Minato-ku, JP;

Masahiro Nomura, Minato-ku, JP;

Kiyoshi Takeuchi, Minato-ku, JP;

Hitoshi Wakabayashi, Minato-ku, JP;

Shigeharu Yamagami, Minato-ku, JP;

Risho Koh, Minato-ku, JP;

Koichi Terashima, Minato-ku, JP;

Katsuhiko Tanaka, Minato-ku, JP;

Masayasu Tanaka, Minato-ku, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.


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