Nonvolatile memory devices having control electrodes configured to inhibit parasitic coupling capacitance

Abstract

Non-volatile memory devices include a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are provided. These first and second floating gate electrodes extend on the first and second semiconductor active regions, respectively. A control electrode is provided that extends between the first and second floating gate electrodes and into the recess in the trench isolation region. The recess in the trench isolation region is sufficiently deep so that the control electrode, which extends into the recess, operates to reduce (e.g., block) a parasitic coupling capacitance between the first and second floating gate electrodes.