The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2010

Filed:

Aug. 15, 2008
Applicants:

Ankur Goel, Bangalore, IN;

Krishman S. Rengarajan, Bangalore, IN;

Sahadevan A. Kumaran, Bangalore, IN;

Sanjay Kumar Mishra, Bangalore, IN;

Inventors:

Ankur Goel, Bangalore, IN;

Krishman S. Rengarajan, Bangalore, IN;

Sahadevan A. Kumaran, Bangalore, IN;

Sanjay Kumar Mishra, Bangalore, IN;

Assignee:

Elpida Memory, Inc., Chuo-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder () for generating a first pre-decoded address (PDA) by pre-decoding the input address (ADD), a CAM circuit () for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit () for outputting a second pre-decoded address (PDA) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer () for selecting either the first or second pre-decoded address (PDAor PDA) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.


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