Method of ensuring the integrity of tlb entries after changing the translation mode of a virtualized operating system without requiring a flush of the tlb

Abstract

Systems and methods are disclosed to support partial physical addressing modes on a virtual machine. An example method disclosed herein identifies a change of a first translation mode to a second translation mode on a host hardware platform, the host hardware platform including a processor, the processor further including region registers; identifies an address as cacheable or non-cacheable; saves contents of the region registers for the first translation mode to processor memory; updates content of the region registers corresponding to the second translation mode; identifies a change of the second translation mode to the first translation mode; and populates the region registers with the contents of the saved region registers corresponding to the first translation mode.