The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2010

Filed:

Oct. 29, 2007
Applicants:

Toshiharu Furukawa, Essex Junction, VT (US);

Mark Charles Hakey, Fairfax, VT (US);

Steven John Holmes, Guilderland, NY (US);

David Vaolav Horak, Essex Junction, VT (US);

Charles William Koburger, Iii, Delmar, NY (US);

Peter H. Mitchell, Jericho, VT (US);

Larry Alan Nesbit, Williston, VT (US);

Inventors:

Toshiharu Furukawa, Essex Junction, VT (US);

Mark Charles Hakey, Fairfax, VT (US);

Steven John Holmes, Guilderland, NY (US);

David Vaolav Horak, Essex Junction, VT (US);

Charles William Koburger, III, Delmar, NY (US);

Peter H. Mitchell, Jericho, VT (US);

Larry Alan Nesbit, Williston, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.


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