The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2010
Filed:
Dec. 23, 2008
Robert J Allen, Jericho, VT (US);
Faye D Baker, Burlington, VT (US);
Albert M Chu, Essex, VT (US);
Michael S Gray, Fairfax, VT (US);
Jason Hibbeler, Williston, VT (US);
Daniel N Maynard, Craftsbury Common, VT (US);
Mervyn Y Tan, Milton, VT (US);
Robert F Walker, St. George, VT (US);
Robert J Allen, Jericho, VT (US);
Faye D Baker, Burlington, VT (US);
Albert M Chu, Essex, VT (US);
Michael S Gray, Fairfax, VT (US);
Jason Hibbeler, Williston, VT (US);
Daniel N Maynard, Craftsbury Common, VT (US);
Mervyn Y Tan, Milton, VT (US);
Robert F Walker, St. George, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.