The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7813189 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 12, 2010

Filed:

Jul. 02, 2008
Applicants:

Yuen Hung Chan, Poughkeepsie, NY (US);

Elspeth Anne Huston, Poughkeepsie, NY (US);

Michael Ju Hyeok Lee, Austin, TX (US);

Inventors:

Yuen Hung Chan, Poughkeepsie, NY (US);

Elspeth Anne Huston, Poughkeepsie, NY (US);

Michael Ju Hyeok Lee, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.


Find Patent Forward Citations

Chan, Yuen. (2010). Array data input latch and data clocking scheme (U.S. Patent No. 7813189). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7813189

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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