The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
Feb. 06, 2007
Brian A. Winstead, Austin, TX (US);
Taras A. Kirichenko, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Rajesh A. Rao, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Ko-min Chang, Austin, TX (US);
Jane Yater, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Taras A. Kirichenko, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Rajesh A. Rao, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Ko-Min Chang, Austin, TX (US);
Jane Yater, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device () by forming a select gate structure () on a first dielectric layer () over a substrate (); forming a control gate structure () on a second dielectric layer () having embedded nanocrystals () so that the control gate () is adjacent to the select gate structure () but separated therefrom by a gap (); forming a floating doped region () in the substrate () below the gap () formed between the select gate structure and control gate structure; and forming source/drain regions () in the substrate to define a channel region that includes the floating doped region ().