The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Aug. 10, 2009
Fulong Zhang, Allentown, PA (US);
Harold Scholz, Allentown, PA (US);
Larry Fenstermaker, Nazareth, PA (US);
John Schadt, Bethlehem, PA (US);
Fulong Zhang, Allentown, PA (US);
Harold Scholz, Allentown, PA (US);
Larry Fenstermaker, Nazareth, PA (US);
John Schadt, Bethlehem, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.