The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Jul. 08, 2008
Hae-rang Choi, Ichon, KR;
Kun-woo Park, Ichon, KR;
Yong-ju Kim, Ichon, KR;
Hee-woong Song, Ichon, KR;
Ic-su OH, Ichon, KR;
Hyung-soo Kim, Ichon, KR;
Tae-jin Hwang, Ichon, KR;
Ji-wang Lee, Ichon, KR;
Hae-Rang Choi, Ichon, KR;
Kun-Woo Park, Ichon, KR;
Yong-Ju Kim, Ichon, KR;
Hee-Woong Song, Ichon, KR;
Ic-Su Oh, Ichon, KR;
Hyung-Soo Kim, Ichon, KR;
Tae-Jin Hwang, Ichon, KR;
Ji-Wang Lee, Ichon, KR;
Hynix Semiconductor Inc., , KR;
Abstract
A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.