The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7808294 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 05, 2010

Filed:

Oct. 15, 2007
Applicant:

Venkata Anil Kottapalli, Fremont, CA (US);

Inventor:

Venkata Anil Kottapalli, Fremont, CA (US);

Assignee:

Netlogic Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A level shifting circuit can include a shift stage that latches first and second internal nodes to opposite shifted logic potentials in response to different transitions at an input signal node. The input signal node can vary between non-shifted logic potentials. An output stage can enable a first controllable impedance path coupled between an output node and a first shifted power supply node in response to a first type transition at the first internal node, and can enable a second controllable impedance path coupled between the output node and a second shifted power supply node in response to the first type transition at the second internal node.


Find Patent Forward Citations

Kottapalli, Venkata. (2010). Level shifter with balanced rise and fall times (U.S. Patent No. 7808294). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7808294

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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