The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Aug. 16, 2006
Chuan-cheng Cheng, Fremont, CA (US);
Choy Hing LI, Saratoga, CA (US);
Shiann-ming Liou, Campbell, CA (US);
Chuan-Cheng Cheng, Fremont, CA (US);
Choy Hing Li, Saratoga, CA (US);
Shiann-Ming Liou, Campbell, CA (US);
Marvell International Ltd., Hamilton, BM;
Abstract
The integrated circuit devices disclosed herein generally include two semiconductor dies. The first die generally has little or no I/O or ESD protection and includes a first plurality of exposed terminals (e.g., bump pads). The second die generally includes (i) a second plurality of exposed terminals, wherein at least one of the second plurality of terminals is in electrical communication with one or more of the first plurality of terminals, (ii) a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with one or more of the second plurality of terminals, and (iii) a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with one or more of the I/O circuits. The present invention advantageously provides the ability to fabricate the second die using different (e.g., less expensive) manufacturing processes than those used to fabricate the first die.