The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Sep. 11, 2007
Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers
Takashi Yamauchi, Kanagawa, JP;
Atsuhiro Kinoshita, Kanagawa, JP;
Yoshinori Tsuchiya, Kanagawa, JP;
Junji Koga, Kanagawa, JP;
Takashi Yamauchi, Kanagawa, JP;
Atsuhiro Kinoshita, Kanagawa, JP;
Yoshinori Tsuchiya, Kanagawa, JP;
Junji Koga, Kanagawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×10atoms/cmor more and yet less than or equal to 1×10atoms/cm. Next, silicidize the p-type layers by reaction with a metal in the state that each layer is applied a compressive strain.