The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2010

Filed:

Aug. 29, 2006
Applicants:

Sreevatsa Sreekantham, West Jordan, UT (US);

Ihsiu Ho, Salt Lake City, UT (US);

Fred Session, Sandy, UT (US);

Kent Naylor, Kaysville, UT (US);

Inventors:

Sreevatsa Sreekantham, West Jordan, UT (US);

Ihsiu Ho, Salt Lake City, UT (US);

Fred Session, Sandy, UT (US);

Kent Naylor, Kaysville, UT (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.


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